2009
Bergveld, H. J.; Nowak, K.; Karadi, R.; Iochem, S.; Ferreira, J.; Ledain, S.; Pieraerts, E.; Pommier, M.
A 65-nm-CMOS 100-MHz 87%-efficient DC-DC down converter based on dual-die system-in-package integration Proceedings
2009, ISBN: 9781424428939, (46).
@proceedings{2-s2.0-72449140593,
title = {A 65-nm-CMOS 100-MHz 87%-efficient DC-DC down converter based on dual-die system-in-package integration},
author = { H.J. Bergveld and K. Nowak and R. Karadi and S. Iochem and J. Ferreira and S. Ledain and E. Pieraerts and M. Pommier},
url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-72449140593&doi=10.1109%2fECCE.2009.5316334&partnerID=40&md5=62791ba9ff207e87242b38d3182b4f7a},
doi = {10.1109/ECCE.2009.5316334},
isbn = {9781424428939},
year = {2009},
date = {2009-01-01},
journal = {2009 IEEE Energy Conversion Congress and Exposition, ECCE 2009},
pages = {3698-3705},
abstract = {The increasing number of efficient voltage conversions realized in small volumes in many applications has introduced a trend towards small-form-factor DC-DC converters with integrated passives. Preferably, the DC-DC converter is integrated with the load, often in nm-CMOS, allowing for local supply optimization yielding increased power efficiency. However, energy-storage densities in nm-CMOS are low and silicon area is expensive. Therefore, to limit cost of monolithically integrated systems, passive components have low values, leading to very high switching frequencies, which compromises efficiency. This paper follows an alternative approach, where the active converter part is realized in 65-nm CMOS and the passive part in a low-cost high-density passive-integration process. With the active die flip-chipped on the passive die a small System-in-Package (SiP) is obtained with a peak efficiency of 87.5% at 100 MHz switching frequency and 85 mW output power. This performance is mainly caused by the high quality of the integrated passives. © 2009 IEEE.},
note = {46},
keywords = {},
pubstate = {published},
tppubtype = {proceedings}
}
The increasing number of efficient voltage conversions realized in small volumes in many applications has introduced a trend towards small-form-factor DC-DC converters with integrated passives. Preferably, the DC-DC converter is integrated with the load, often in nm-CMOS, allowing for local supply optimization yielding increased power efficiency. However, energy-storage densities in nm-CMOS are low and silicon area is expensive. Therefore, to limit cost of monolithically integrated systems, passive components have low values, leading to very high switching frequencies, which compromises efficiency. This paper follows an alternative approach, where the active converter part is realized in 65-nm CMOS and the passive part in a low-cost high-density passive-integration process. With the active die flip-chipped on the passive die a small System-in-Package (SiP) is obtained with a peak efficiency of 87.5% at 100 MHz switching frequency and 85 mW output power. This performance is mainly caused by the high quality of the integrated passives. © 2009 IEEE.
Roozeboom, F.; Bergveld, H. J.; Nowak, K.; Cornec, F. Le; Guiraud, L.; Bunel, C.; Iochem, S.; Ferreira, J.; Ledain, S.; Pieraerts, E.; Pommier, M.
Ultrahigh-density trench capacitors in silicon and their application to integrated DC-DC conversion Proceedings
vol. 1, no. 1, 2009, ISSN: 18766196, (5).
@proceedings{2-s2.0-71549167984,
title = {Ultrahigh-density trench capacitors in silicon and their application to integrated DC-DC conversion},
author = { F. Roozeboom and H.J. Bergveld and K. Nowak and F. Le Cornec and L. Guiraud and C. Bunel and S. Iochem and J. Ferreira and S. Ledain and E. Pieraerts and M. Pommier},
url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-71549167984&doi=10.1016%2fj.proche.2009.07.358&partnerID=40&md5=fb04f63a8818853aed362607bbea4404},
doi = {10.1016/j.proche.2009.07.358},
issn = {18766196},
year = {2009},
date = {2009-01-01},
journal = {Procedia Chemistry},
volume = {1},
number = {1},
pages = {1435-1438},
abstract = {This paper addresses silicon-based integration of passive components applied to 3D integration with dies of other technologies within one package. Particularly, the development of high-density trench capacitors has enabled the realization of small-formfactor DC-DC converters. As illustration, an integrated inductive DC-DC converter based on flip-chipping a 65-nm CMOS active die on a PICS™ (Passive-Integration Connecting Substrate) passive die is described. The PICS die includes high-density (80 nF/mm2) integrated MOS trench capacitors. A converter peak efficiency of 87.5% is achieved at Vin=1.2 V},
note = {5},
keywords = {},
pubstate = {published},
tppubtype = {proceedings}
}
This paper addresses silicon-based integration of passive components applied to 3D integration with dies of other technologies within one package. Particularly, the development of high-density trench capacitors has enabled the realization of small-formfactor DC-DC converters. As illustration, an integrated inductive DC-DC converter based on flip-chipping a 65-nm CMOS active die on a PICS™ (Passive-Integration Connecting Substrate) passive die is described. The PICS die includes high-density (80 nF/mm2) integrated MOS trench capacitors. A converter peak efficiency of 87.5% is achieved at Vin=1.2 V